This invention pertains to a manufacturing method of a semiconductor IC device. In particular, this invention pertains to a manufacturing method of a semiconductor IC device having connecting holes or trenches with a high dimensional precision and fine configuration.
The present inventors have surveyed the manufacturing methods of the semiconductor IC device. The following is a summary of the technologies surveyed by the present inventors.
In DRAM (Dynamic Random Access Memory) having the so-called capacitor-over-bit line (COB) type of memory cells with capacitors for storing information set above the bit lines, after formation of the bit lines (BL), an electrical connection occurs between the lower electrodes of the capacitor (storage node electrode, storing electrode) and the semiconductor region that becomes the drain of the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in the semiconductor substrate. For this purpose, connecting holes are formed on the insulating film made of silicon in the area between them.
In this case, with the progress in miniaturization, it has become more difficult to ensure the alignment tolerance between the aforementioned connecting holes and the bit lines. Consequently, studies have been performed on the technology used to form the aforementioned connecting holes in a self-aligned manner along the step of the said bit lines by covering said bit lines with a silicon nitride film, and using the silicon nitride film as an etching stopper film in the dry etching processing for forming the aforementioned connecting holes on the silicon nitride film.
For example, Japanese Kokai Patent Application No. Hei 3[1991]-214669 disclosed a type of semiconductor IC device having DRAM.
However, when the aforementioned connecting holes are formed, the silica film is dry-etched and the hole-opening property is improved. In this case, the etching selectivity for the silicon nitride film that covers the bit lines is degraded, so that the connecting holes come in contact with the bit line and the formation operation of the connecting holes becomes incomplete.
Consequently, it was once proposed that the thickness of the silicon nitride film covering the bit lines be increased. However, in this case, due to the stress of the silicon nitride film, the bit lines and the semiconductor substrate, as well as the MOSFET and various other structural elements formed on the substrate undergo deformation.
The purpose of this invention is to provide a technology that allows the formation of connecting holes and trenches having high dimensional precision and fine structure.
The aforementioned purpose and other purposes of this invention will be explained in the following with reference to the text and FIGS. of this specification.
1 represents a semiconductor substrate (substrate), 1a a trench, 2 a silica film (insulating film), 2a a trench, 2b an opening, 3 a polysilicon film (first mask film), 4 a resist film, 5 a polysilicon film (second mask film), 5a a polysilicon film (side wall), 6 a silica film (insulating film), 6a a silica film (separating film), 7 a gate insulating film, 8 a gate electrode, 9 an insulating film, 10 a side-wall insulating film (side wall spacer), 11 a gate region, 12 a semiconductor region, 13 a silica film, 14 a plug, 15 a silica film (insulating film), 16 a wiring layer, 17 a silica film (insulating film), 17a a trench, 18 a polysilicon film (first mask film), 19 a resist film, 20 a polysilicon film (second mask film), 20a a polysilicon film (side wall), 21 a connecting hole, 22 a plug, 23 a lower electrode of capacitor, 24 a dielectric film of capacitor, 25 an upper electrode of capacitor, 26 a Silica film (insulating film), 26a a trench, 27 a polysilicon film (first mask film), 28 a resist film, 29 a polysilicon film (second mask film), 29a a polysilicon film (side wall), 30 a trench, 31 an aluminum layer (electroconductive layer), 31a an aluminum layer (wiring layer).
The following is a brief explanation of the invention disclosed in this patent application.
The manufacturing method of a semiconductor IC device of this invention comprises the following steps of operation:
a step in which an insulating film is formed on a semiconductor substrate or SOI substrate;
a step in which a first mask film is formed on the aforementioned insulating film;
a step in which, after a resist film is formed on the aforementioned first mask film, the resist film is used as an etching mask to form an opening on the aforementioned first mask film, followed by the formation of trenches on the aforementioned insulating film exposed from the opening;
a step in which, after the aforementioned resist film is removed, a second mask film is formed on the aforementioned semiconductor substrate or SOI substrate;
a step in which, by removing the aforementioned second mask film such that it is left on the side walls of the aforementioned trenches, a side wall made of the aforementioned second mask film is formed on the side walls of the aforementioned trenches;
and a step in which the aforementioned first mask film and the aforementioned side wall are used as the etching mask in etching off the aforementioned insulating film exposed from the mask, so as to form connecting holes on the aforementioned insulating film.
This invention also provides a manufacturing method of semiconductor IC device, characterized by the fact that it consists of the following steps of operation:
a step in which an insulating film is formed on a semiconductor substrate or SOI substrate;
a step in which a first mask film is formed on the aforementioned insulating film;
a step in which, after a resist film is formed on the aforementioned first mask film, the resist film is used as an etching mask to form an opening on the aforementioned first mask film, followed by the formation of trenches on the aforementioned insulating film exposed from the opening;
a step in which, after the aforementioned resist film is removed, a second mask film is formed on the aforementioned semiconductor substrate or SOI substrate;
a step in which, by removing the aforementioned second mask film such that it is left on the side walls of the aforementioned trenches, a side wall made of the aforementioned second mask film is formed on the side walls of the aforementioned trenches;
a step in which the aforementioned first mask film and the aforementioned side wall are used as the etching mask in etching off the aforementioned insulating film exposed from the mask, so as to form an opening on the aforementioned insulating film, followed by the formation of separating trenches on the aforementioned semiconductor substrate or SOI substrate exposed from the opening;
and a step in which an insulating film is buried in the aforementioned separating trenches to form a separating portion.
This invention also provides a manufacturing method of a semiconductor IC device characterized by the fact that it consists of the following steps of operation:
a step in which an insulating film is formed on a semiconductor substrate or SOI substrate;
a step in which a first mask film is formed on the aforementioned insulating film;
a step in which, after a resist film is formed on the aforementioned first mask film, the resist film is used as an etching mask to form an opening on the aforementioned first mask film, followed by the formation of trenches on the aforementioned insulating film exposed from the opening;
a step in which, after the aforementioned resist film is removed, a second mask film is formed on the aforementioned semiconductor substrate or SOI substrate;
a step in which, by removing the aforementioned second mask film such that it is left on the side walls of the aforementioned trenches, a side wall made of the aforementioned second mask film is formed on the side walls of the aforementioned trenches;
and a step in which the aforementioned first mask film and the aforementioned side wall are used as the etching mask in etching off the aforementioned insulating film exposed from the mask, so as to form wiring-forming trenches on the aforementioned insulating film, followed by burying an electroconductive material in the aforementioned wiring-forming trenches to form a wiring layer made of the electroconductive material.
The following is a brief account of the typical effects of the invention disclosed in this patent application.
(1) In the manufacturing method of the semiconductor IC device of this invention, in order to make an electrical connection between the lower electrodes of the capacitors of the COB-type memory cell in DRAM and the plugs on the semiconductor region as the drain of the MOSFET formed on a semiconductor substrate or other substrate, connecting holes are formed on the silica film or other insulating film in the area between them, followed by the formation of plugs in the connecting holes.
In this case, the hook-shaped hard mask is used in performing the etching operation to form the connecting holes. Consequently, it is possible to etch and form the side surfaces of the connecting holes in the vertical direction while the pattern dimensions of the hook-shaped hard mask are maintained. As a result, even when the connecting holes are deep, it is still possible to form the connecting holes with processing dimensions finer than the processing limit in the conventional case involving the formation of connecting holes using photolithographic technology and selective etching technology without using the hook-shaped hard mask, and it is possible to form the connecting holes in fine processing with a high dimensional precision. In this case, according to studies performed by the present inventors, even when the aspect ratio of the connecting holes is 3 or larger, it is still possible to form fine-structure connecting holes having vertical side surfaces.
Consequently, it is possible to prevent the problem of contact between the connecting holes and the wiring layer as bit lines adjacent to the connecting holes, so that it is possible to provide a type of semiconductor IC device with a high performance and high manufacturing yield, as well as its manufacturing method.
(2) Using the manufacturing method of the semiconductor IC device of this invention, it is possible to form the element-separating insulating film made of silica film, etc., buried in trenches in a selected region of the semiconductor substrate or other substrate, and it is possible to form the element-separating insulating film having a plane flush with the surface of the substrate in the region of the flattened semiconductor substrate or other substrate.
In this case, the hook-shaped hard mask is used in performing the etching operation to form the opening on the insulating film in the lower portion of the hook-shaped hard mask and to form trenches on the substrate. Consequently, it is possible to etch and form the side surfaces of the opening and trenches in the vertical direction while the pattern dimensions of the hook-shaped hard mask are maintained. As a result, even when the trenches are deep, it is still possible to form the trenches with processing dimensions finer than the processing limit in the conventional case involving the formation of trenches using photolithographic technology and selective etching technology without using the hook-shaped hard mask. It is also possible to form the trenches in fine processing with a high dimensional precision.
Consequently, it is possible to form an element-separating film having fine-structure trenches, so that is it possible to provide a type of semiconductor IC device with a high performance and high manufacturing yield, as well as its manufacturing method.
(3) Using the manufacturing method of the semiconductor IC device of this invention, it is possible to form a wiring layer (damassin wiring layer) buried in the trenches on a silica film or other insulating film, and it is possible to form a wiring layer having a plane flush with the surface of the region of the flattened silica film or other insulating film.
In this case, the hook-shaped hard mask is used in performing the etching operation to form the trenches. Consequently, it is possible to etch and form the side surfaces of the trenches in the vertical direction while the pattern dimensions of the hook-shaped hard-mask are maintained. As a result, even when the trenches are deep, it is still possible to form the trenches with processing dimensions finer than the processing limit in the conventional case involving the formation of trenches using photolithographic technology and selective etching technology without using the hook-shaped hard mask, and it is possible to form the trenches in fine processing with a high dimensional precision.
Consequently, it is possible to form the wiring layer having fine-structure trenches, so that is it possible to provide a type of semiconductor IC device with a high performance and high manufacturing yield, as well as its manufacturing method.